The present invention relates to the field of electronic devices having embedded memory, and is more specifically directed to the testing and repairing of the embedded memory.
Embedded memory is memory that is embedded with a processor. The embedded memory can be the memory necessary for the core functionality of the processor, it can also be the data storage memory, where the data that the processor processes is stored. Many processors contain a small amount of memory, typically on the order of several kilo bits, which is typically arranged into memory registers and is necessary for the core functionality of the processor.
The data storage memory is much larger than the memory that is needed for the processor for its core functionality. Currently this memory is usually external memory, i.e. it is not embedded on the same integrated circuit that the processor is on because of the low yield of the process in manufacturing the circuit and the expense of testing and repairing the memory. A goal in the semiconductor industry is to increase the speed of the processor. One way to increase the speed of the processor is to embed the memory used for data storage into the processor.
When memory used for data storage is on a separate chip than the processor the two chips must be electrically coupled. The input/output pins of the processor are coupled to the input/output pins of the memory by external metal connections. This increases the amount of time it takes for the processor to read data out of the memory and write data into the memory. Embedding the memory into the processor reduces the amount of time the processor takes to access the memory. Additionally, since the memory now does not require the external input/output pins previously needed for coupling to the processor, the packaging cost of the memory is greatly reduced. Furthermore, the memory can now be specifically configured for the processor into which it is embedded. Embedding the memory in the processor also eliminates the need for the external metal connections, increasing the accuracy of the connections in the combined product.
For example, a standard memory device design can be embedded in the processor, with the memory array and peripheral circuits needed to operate the memory array coupled to the processor. Since most standard memory devices have input/output pads, the embedded memory would have the input/output pads but they would be disconnected from the memory array and memory peripheral circuits. Although, since the input/output pads are disconnected from the memory array and peripheral circuits, they are not necessary for the functioning of the memory and may be removed. This frees up the space previously occupied by these pads, thereby reducing the total size of the memory. However, this would require a memory devices manufactured without the input/output pads.
Both the memory and the processors are tested to ensure that they do not malfunction. Every cell in a memory is typically tested to ensure that there are no defective cells. A fatal defect in one memory cell makes the cell inoperable. If the cell is not replaced the entire memory device can malfunction. Therefore, a defective memory cell must either be replaced, or the entire chip discarded. When the memory is embedded in a processor the cost of discarding the chip increases.
As the component size is reduced and the density of components per unit area of a semiconductor device is increased, the costs of the device decreases while its speed increases. However, as the size of components decreases and their density increases the size of a defect that can cause failure also shrinks. Additionally, as the speed with which processors process data increases, the amount of data that can be made available to the processors also increases, usually by increasing the size of the memory for storing data. As the size of and total number of components in a memory device continues to increase, so does the cost of each memory device, and therefore the cost of each non-usable memory device.
Redundant columns and/or rows are often used in memory devices to prevent an isolated defect from destroying the entire device. The decision on whether to use redundant columns and/or rows is based on balancing the additional die space needed for the redundancy architecture and the yield of the manufacturing process if redundancy is not used. If the yield is high enough, it is cheaper to discard the few memories with defective cell than add the redundancy architecture to each memory. If the yield is not sufficiently high, the redundancy architecture can greatly decrease the yield loss in these memory devices by replacing a column or row containing a defect in one of its memory cells with a redundant column or row. This can save a memory device that would otherwise have been unusable.
The defects in the memory cells are discovered in initial testing, and the redundant columns or rows can then be activated to replace the columns or rows containing defective cells. Extensive testing is performed on the memory to determine which if any of the memory cells are defective. The test equipment for testing memories is coupled to the input/output pads of the memory. When a memory is embedded into the processor this is usually is not possible. There are either no external input/output pads on the memory for the test equipment to connect to; or some external input/output pads remain, but not enough to test every memory cell. Thus the memory must be tested through the processor.
Processors are also tested to ensure that they function properly. The test equipment for testing processors is coupled to the input/output pads of the processor.
A problem in the prior art is that the cost of testing a chip increases when a memory is embedded in a processor. This is especially true for the testing required to discover which memory cell is defective. To find exactly which memory cell is defective the memory must be extensively tested. In modern technology, embedded memory is tested through the processor, using the input/output pads of the processor since the memory does not have, or does not have enough of, its own input/output pads. The testing equipment for the processors is at least several times more expensive than comparable testing equipment for memories. Both the memory and the processor must now be tested on the processor testing equipment, increasing the amount of time each chip is required to spend on the processor testing equipment by the amount of time it takes to perform the memory tests. Therefore, either:
(1) more very expensive processor testing equipment must be used to test both the processor and the memories which can now only be tested through the processor, drastically increasing the cost of each chip; or PA1 (2) the cycle time of producing a given number of processors containing embedded memories will be much larger than for processors without embedded memories.
Both of these increase the cost of the chip, whether the memory will be repaired or not, since either way each memory cell must still be tested. Although when the memory will also be repaired the test time and therefore the cost is even greater. When the memory is small this increase is small. However, when the memory is the size of a memory used for data storage, which can range from hundreds of kilo bits to many Mega bits or more, this increase is prohibitively expensive. This makes the cost of embedding memories for data storage into processor impractical despite all the advantages, described above, obtained from embedding the memory into the processor, and hinders the achievement of the long recognized goal to increase the speed with which the processor can access data.